In a multi-cabinet computer system with on-line serviceability, it is entirely possible for some electronic (circuits) to be powered from the system""s power subsystem and for other circuits to be unpowered. This situation can also occur when circuits and/or sub-units of the system receive power supply from different sources. This can cause problems when signals are driven by CMOS circuits to CMOS receiver circuits that are unpowered. A CMOS output driver trying to drive an unpowered CMOS receiver could cause severe damage to the driving transistor due to the essentially short circuit current paths presented by the unpowered circuit. This is illustrated in FIG. 1, showing a driving circuit (Q1D, Q2D p channel, n-channel, respectively) coupled to a receiving circuit (Q1R, Q2R p channel, n-channel, respectively) by a conductor 10. (The circuits Q1D, Q2D and Q1R, Q2R may, for example, be carried by a circuit board (not shown) or an integrated circuit on a circuit board.) The driving circuit, Q1D, Q2D, and receiving circuit, D1R, Q2R, reside in different power zones and are respectively connected to a different power supply. The receiving circuit is connected to its respective power supply (P.S.) along with other circuits on the board or integrated circuit. If the driving and receiving circuits are CMOS construction, the receiving circuits Q1R, Q2R will have parasitic diodes D1, D2 formed between their gate leads and their respective drain leads.
Now, suppose that the receiver circuit Q1R, Q2R is unpowered. If the driver circuit Q1D, Q2D is tuned on for communication, the transistor Q1D will conduct. However, since the power supply P.S. is not yet powered, it will be in essentially a low impedance state, as will the other circuits (xe2x80x9cLoadxe2x80x9d) associated with the receiver circuit Q1R, Q2R. Turning on Q1D will apply Vdd(1) to the gate lead of Q1R to turn on its associated parasitic diode D1, creating a low impedance path from the supply voltage (Vdd(1)) of the driver circuit (Q1, Q2D), through the parasitic diode D1, and the parallel (low) impedance presented by the power supply and load associated with the receiver circuit Q1R, Q2R. The resultant excessive current flow permitted by the low impedance path can cause long-term reliability problems in the driving circuit if allowed to persist. The addition of electrostatic discharge ESD) protection diodes (not shown) as are typically used will only exacerbate this problem.
One approach to avoiding this problem is to provide a power line that communicates the xe2x80x9cpower onxe2x80x9d state from the receiver circuit to the driver circuit, informing the latter that the receiver circuit has power. This will require a dedicated pin and conductor at each end for this purpose. (Usually, the communication is bi-lateral, so that a similar power signal is communicated from the driver end. Thus, if the driver and receiver circuits are in different power zones, as FIG. 1 illustrates, two conductors and associated pins must be used.) In many complex circuits/systems, such an extravagant use of pins and conductors is costly.
The invention provides a simple and relatively inexpensive mechanism that avoids dedicating use of a signal line (and associated pins at each end) to provide an indication in one power zone that at another power zone a circuit at the transmitting end or side is powered. Broadly, the invention transmits a periodic (e.g., clock) signal to indicate that power is available at the transmitting end or side. Conversely, at the receiver side a detector listens for such a clock signal to determine if the other (transmitting) side is powered or not.
The present invention is directed to use in which elements of systems reside in different power zones (i.e., they receive supply power from different sources). One aspect of the invention has a driver circuit initially sending a clock signal across power zones to a receiving side to indicate that the transmitting side is powered. A detected absence of the clock signal at the receiving side will cause all output driver circuits of the receiving side coupled to the transmitting side to be disabled, i.e., placed in a high-impedance or off state, to prevent the driver circuits from operating into a low impedance load of a powered-down circuit.
According to another aspect of the invention, the transmitting side will periodically send short bursts of the clock signal while holding all other driver circuits of the transmitting side in the high-impedance state to inform the receiving side that the transmitting side is powered-up. At the same time, the transmitting side monitors its receiver circuitry to detect a similar clock signal from the receiving side, indicating a powered condition.
According to another aspect of the invention, the transmitting side will place those driver circuits coupled to the receiving end in an enabled state when a clock signal is detected as being sent by the receiving side.
According to another aspect of the invention, after detection of a clock signal from the receiving side, the transmitting side continues to drive its output circuits regardless of whether a clock signal continues to be received from the receiving side until a predetermined delay expires.
Other features and advantages of the invention will be apparent in view of the following detailed description and appended drawings.